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?2013 fairchild semiconductor corporation 1 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 fsb50760sf, FSB50760SFT moti on spm? 5 superfet? series may 2013 fsb50760sf, FSB50760SFT motion spm ? 5 superfet ? series features ? ul certified no. e209204 ? 600 v r ds(on) = 530 m ?? max ? superfet mosfet 3- phase inverter including hvics ? three separate open-source pins from low side mosfets for three l eg current sensing ? hvic for gate driving and undervoltage protection ? active-high interface, can work with 3.3 v / 5 v logic ? optimized for low electromagnetic interference ? isolation voltage rating of 1500 vrms for 1 min. ? temperature sensing built in hvic ? embedded bootstrap diode in the package ? rohs compliant applications ? 3-phase inverter driver for small power ac motor drives general description fsb50760sf and FSB50760SFT are a motion spm ? 5 superfet ? series based on super junction mosfet (superfet) technology as a compact inverter solution for small power motor drive applications such as refrigerators, fans and pumps. fsb50760sf and FSB50760SFT contains six superfet mosfets, three half-bridge gate driv e hvics with temperature sensing, and three bootstrap diodes in a compact package fully isolated and optimized for thermal performance. esoecially, adopted superfet mosfets have fast trr characteristics for body-diode. fsb50- 760sf and FSB50760SFT features low electro- magnetic interference(emi) characteristics through optimizing switching speed and reducing parasitic inductance. since fsb50760sf and FSB50760SFT employs mosfets as power switches, it povides much more ruggedness and larger safe operating area (soa) than igbt-based power modules. fsb50760sf and FSB50760SFT are the right solution for compact and reliable inverter designs where the assembly space is constrained. related resources ? rd-fsb50450a : reference design for motion spm 5 series ver.2 ? an-9082 : motion spm 5 se ries thermal performance by contact pressure package marking & ordering information device marking device package reel size packing type quantity fsb50760sf fsb50760sf spm5p-023 - rail 15 FSB50760SFT FSB50760SFT spm5n-023 - rail 15 fsb50760sf FSB50760SFT
fsb50760sf, FSB50760SFT motion spm? 5 superfet? series ?2013 fairchild semiconductor corporation 2 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 absolute maximum ratings inverter part (each mosfet unless otherwise specified) control part (each hvic unless otherwise specified) bootstrap diode part (each bootstrap diode unless otherwise specified) thermal resistance total system note: 1. for the measurement point of case temperature t c , please refer to figure 4. 2. marking ? * ? is calculation value or design factor. symbol parameter conditions rating unit v pn dc link input voltage, drain-source voltage of each mosfet 600 v *i d 25 each mosfet drain current, continuous t c = 25c 3.6 a *i d 80 each mosfet drain current, continuous t c = 80c 2.7 a *i dp each mosfet drain current, peak t c = 25c, pw < 100 ? s 9.4 a *i drms each mosfet drain current, rms t c = 80c, f pwm < 20 khz 1.9 a rms *p d maximum power dissipation t c = 25c, for each mosfet 14.5 w symbol parameter conditions rating unit v cc control supply voltage applied between v cc and com 20 v v bs high-side bias voltage applied between v b and v s 20 v v in input signal voltage applied between in and com - 0.3 ~ v cc + 0.3 v symbol parameter conditions rating unit v rrmb maximum repetitive reverse voltage 600 v * i fb forward current t c = 25c 0.5 a * i fpb forward current (peak) t c = 25c, under 1ms pulse width 1.5 a symbol parameter conditions rating unit r ? jc junction to case thermal resistance each mosfet under inverter oper- ating condition (note 1) 8.6 c/w symbol parameter conditions rating unit t j operating junction temperature -40 ~ 150 c t stg storage temperature -40 ~ 125 c v iso isolation voltage 60 hz, sinusoidal, 1 minute, con- nection pins to heatsink 1500 v rms
fsb50760sf, FSB50760SFT motion spm? 5 superfet? series ?2013 fairchild semiconductor corporation 3 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 pin descriptions note: source terminal of each low-side mosfet is not connected to supply ground or bias voltage ground inside motion spm ? 5 products. external connections should be made as indicated in figure 3 figure 1. pin configuration and in ternal block diag ram (bottom view) pin number pin name pin description 1 com ic common supply ground 2v b(u) bias voltage for u phase high side mosfet ? driving 3v cc(u) bias voltage for u phase ic and low side mosfet driving 4in (uh) signal input for u phase high-side 5in (ul) signal input for u phase low-side 6n.cn.c 7v b(v) bias voltage for v phase high side mosfet driving 8v cc(v) bias voltage for v phase ic and low side mosfet driving 9in (vh) signal input for v phase high-side 10 in (vl) signal input for v phase low-side 11 v ts output for hvic temperature sensing 12 v b(w) bias voltage for w phase high side mosfet driving 13 v cc(w) bias voltage for w phase ic and low side mosfet driving 14 in (wh) signal input for w phase high-side 15 in (wl) signal input for w phase low-side 16 n.c n.c 17 p positive dc?link input 18 u, v s(u) output for u phase & bias voltage ground for high side mosfet driving 19 n u negative dc?link input for u phase 20 n v negative dc?link input for v phase 21 v, v s(v) output for v phase & bias voltage ground for high side mosfet driving 22 n w negative dc?link input for w phase 23 w, v s(w) output for w phase & bias voltage ground for high side mosfet driving (1) com (2) v b(u) (3) v cc(u) (4) in (uh) (5) in (ul) (6) n.c (7) v b(v) (8) v cc(v) (9) in (vh) (10) in (vl) (11) v ts (12) v b(w) (13) v cc(w) (14) in (wh) (15) in (wl) (16) (17) p (18) u, v s(u) (19) n u (20) n v (21) v, v s(v) (22) n w (23) w, v s(w) com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo v ts com vcc lin hin vb ho vs lo n.c
fsb50760sf, FSB50760SFT motion spm? 5 superfet? series ?2013 fairchild semiconductor corporation 4 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 electrical characteristics (t j = 25c, v cc =v bs = 15 v unless otherwise specified) inverter part (each mosfet unless otherwise specified) control part (each hvic unless otherwise specified) bootstrap diode part (each bootstrap diode unless otherwise specified) note: 1. bv dss is the absolute maximum voltage rating between drain and source terminal of each mosfet inside motion spm ? 5 products. v pn should be sufficiently less than this value considering the effect of the stray inductance so that v ds should not exceed bv dss in any case. 2. t on and t off include the propagation delay time of the internal drive ic. listed values are measured at the laboratory test condition, and they can be different according to the field applications due to the effect of different printed circuit boards and wirings. please see figure 6 for the switch ing time definition with the switching test circuit of figure 7. 3. the peak current and voltage of each mosfet during the switching operation should be included in the safe operating area (so a). please see figure 7 for the rbsoa test circuit that is same as the switching test circuit. 4. v ts is only for sensing temperature of module and cannot shutdown mosfets automatically. 5. built in bootstrap diode includes around 15 ? resistance characteristic. please refer to figure 2. symbol parameter conditions min typ max unit bv dss drain-source breakdown voltage v in = 0v, i d = 1 ma (note 1) 600 - - v i dss zero gate voltage drain current v in = 0v, v ds = 600 v - - 1 ma r ds(on) static drain-source on-resistance v cc = v bs = 15 v, v in = 5 v, i d = 2 a - 460 530 m ? v sd drain-source diode forward voltage v cc = v bs = 15v, v in = 0v, i d = - 2 a - - 1.1 v t on switching times v pn = 300 v, v cc = v bs = 15 v, i d = 2 a v in = 0 v ? 5 v, inductive load l= 3 mh high- and low-side mosfet switching (note 2) - 1200 -ns t off - 970 -ns t rr - 160 -ns e on - 120 - ? j e off - 10 - ? j rbsoa reverse-bias safe oper- ating area v pn = 400 v, v cc = v bs = 15 v, i d = i dp , v ds =bv dss , t j = 150c high- and low-side mosfet switching (note 3) full square symbol parameter conditions min typ max unit i qcc quiescent v cc current v cc =15 v, v in =0v applied between v cc and com - - 200 ? a i qbs quiescent v bs current v bs =15 v, v in =0v applied between v b(u) -u, v b(v) -v, v b(w) -w - - 100 ? a uv ccd low-side undervoltage protection (figure 8) v cc undervoltage protection detection level 7.4 8.0 9.4 v uv ccr v cc undervoltage protection reset level 8.0 8.9 9.8 v uv bsd high-side undervoltage protection (figure 9) v bs undervoltage protection detection level 7.4 8.0 9.4 v uv bsr v bs undervoltage protection reset level 8.0 8.9 9.8 v v ts hvic temperature sens- ing voltage output v cc = 15 v, t hvic = 25c (note 4) 600 790 980 mv v ih on threshold voltage logic high level applied between in and com --2.9v v il off threshold voltage logic low level 0.8 - - v symbol parameter conditions min typ max unit v fb forward voltage i f = 0.1 a, t c = 25c (note 5) - 2.5 - v t rrb reverse recovery time i f = 0.1 a, t c = 25c - 80 - ns
fsb50760sf, FSB50760SFT motion spm? 5 superfet? series ?2013 fairchild semiconductor corporation 5 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 recommended operating condition figure 2. built in bootstrap diode characteristics (typ.) symbol parameter conditions value unit min. typ. max. v pn supply voltage applied between p and n - 300 400 v v cc control supply voltage applied between v cc and com 13.5 15 16.5 v v bs high-side bias voltage applied between v b and v s 13.5 15 16.5 v v in(on) input on threshold voltage applied between in and com 3.0 - v cc v v in(off) input off threshold voltage 0 - 0.6 v t dead blanking time for preventing arm-short v cc =v bs = 13.5 ~ 16.5 v, t j ?? 150c 1 - - ? s f pwm pwm switching frequency t j ?? 150c - 20 - khz 0123456789101112131415 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 built in bootstrap diode v f -i f characteristic i f [a] v f [v] tc=25c
fsb50760sf, FSB50760SFT moti on spm? 5 superfet? series ?2013 fairchild semiconductor corporation 6 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 note: 1. parameters for bootstrap circuit elements are dependent on pwm algorithm. for 15 khz of switching frequency, typical example of parameters is shown above. 2. rc coupling (r 5 and c 5 ) and c 4 at each input of motion spm 5 product and micom (indicated as dotted lines) may be used to prevent improper signal due to surg e noise. 3. bold lines should be short and thick in pcb pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. bypass capacitors such as c 1 , c 2 and c 3 should have good high-frequency characterist ics to absorb high-frequency ripple current. figure 3. recommended mcu interface and bootst rap circuit wit h parameters note: attach the thermocouple on top of the heatsink-side of spm 5 package (between motion spm 5 products and heatsink if applied) to get the correct temperature measurement. figure 4. case temperature measurement figure 5. temperature profile of v ts (typ.) hin lin output note 0 0 z both frfet off 0 1 0 low side frfet on 10 v dc high side frfet on 1 1 forbidden shoot through open open z same as (0,0) com vcc lin hin vb ho vs lo p n r 3 inverter output c 3 c 1 micom 15 v line 10 ? f one leg diagram of motion spm ? 5 product these values depend on pwm control algorithm * example of bootstrap paramters : c 1 = c 2 = 1 ? f ceramic capacitor r 5 c 5 v dc c 2 v ts * example circuit : v phase c 4 v ? 20 40 60 80 100 120 140 160 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v ts [v] t hvic [deg]
fsb50760sf, FSB50760SFT motion spm? 5 superfet? series ?2013 fairchild semiconductor corporation 7 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 figure 6. switching time definitions figure 7. switching and rbsoa (si ngle-pulse) test circuit (low-side) figure 8. undervoltage protection (low-side) figure 9. undervoltage protection (high-side) t on t rr i rr 100% of i d 120% of i d (a) turn-on t off (b) turn-off i d v ds v ds i d v in v in 10% of i d com vcc lin hin vb ho vs lo one leg diagram of motion spm ? 5 product i d v cc c bs lv dc + v ds - v ts uv ccd uv ccr input signal uv protection status low-side supply, v cc mosfet current reset detection reset uv bsd uv bsr input signal uv protection status high-side supply, v bs mosfet current reset detection reset
fsb50760sf, FSB50760SFT motion spm? 5 superfet? series ?2013 fairchild semiconductor corporation 8 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 note: 1. about pin position, refer to figure 1. 2. rc coupling (r 5 and c 5 , r 4 and c 6 ) and c 4 at each input of motion spm ? 5 products and micom are useful to prevent improper input signal caused by surge noise. 3. the voltage drop across r 3 affects the low side switching performance and the bootstrap characteristics since it is placed between com and the source ter minal of the low side mosfet. for this reason, the voltage drop across r 3 should be less than 1 v in the steady-state. 4. ground wires and output terminals, should be thick and short in order to avoid surge voltage and malfunction of hvic. 5. all the filter capacitors should be connected close to motion spm 5 products, and they should have good characteristics for rejecting high-frequency ripple current. figure 10. example of application circuit com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo (1 ) com (2 ) v b(u) (3 ) v cc(u) (4 ) in (uh) (5 ) in (ul) (6 ) n.c (7 ) v b(v) (8 ) v cc(v) (9 ) in (vh) (10) in (vl) (11) v ts (12) v b(w) (13) v cc(w) (14) in (wh) (15) in (wl) (16) n.c (17) p (18) u, v s(u) (19) n u (22) n w micom c 1 15- v supply c 3 v dc c 2 r 3 r 4 c 6 r 5 c 5 for current sensing and protection v ts (21) v, v s(v) (20) n v (23) w, v s(w) c 4 m
fsb50760sf, FSB50760SFT motion spm? 5 superfet? series ?2013 fairchild semiconductor corporation 9 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 detailed package outline drawings (fsb50760sf) dimension unit : [mm]
fsb50760sf, FSB50760SFT moti on spm? 5 superfet? series ?2013 fairchild semiconductor corporation 10 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1 detailed package outline drawings (FSB50760SFT) dimension unit : [mm]
fsb50760sf, FSB50760SFT moti on spm? 5 superfet? series ?2013 fairchild semiconductor corporation 11 www.fairchildsemi.com fsb50760sf, FSB50760SFT rev. c1

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